1. Field of the Invention
The present invention relates to a circuit arrangement or circuit configuration including high-performance rectifiers and low inductance. In particular the present invention relates to a circuit arrangement having high-performance rectifiers using semiconductor switches to minimize operation time, minimize power loss, and parasitic inductance.
2. Description of the Related Art
The prior art has recognized the desirability to reduce operation time and reduce power loss. It is known that circuit arrangements including MOSFETs (metallic oxide semiconductor field-effect transistors) or IGBTs (insulated gate bipolar transistors) with antiparallel-connected free-running diodes are well suited to operate relatively quickly and with reduced power loss.
The circuit arrangements include rectifiers and must be of low-inductance design to prevent the generation of voltage spikes. The voltage spikes especially occur during power-off operation. This means that to minimize voltage spikes, circuit arrangements must have low leakage inductances in an intermediate circuit, on connecting leads, and on the substrate surface itself. In the case of low-voltage MOSFETs, even leakage inductances in the 20 nH (nanohenry) range may lead to voltage spikes which can destroy the semiconductor switches.
There are many prior art examples including individual and semiconductor modules with individual design features specifically directed to reduce parasitic inductance. Examples of these are EP 0277 546, DE 39 37 045, and EP 0 609 528.
EP 0 277 546 describes a method of reducing parasitic inductances in the direct-current leads of individual switches. In this reference, two DC leads are arranged in close proximity and are at least partly parallel to each other. This arrangement causes a small current-diffuse area in a region of closely adjacent leads, and this sector of the leads is therefore of low inductance.
DE 39 37 045 describes a method for reducing parasitic inductances in the DC leads of a half-bridge. In this reference, two DC leads are in close proximity, but with an AC lead between the positive and negative lines. The leads are at least partly parallel to each other. This causes a reduction in size of the current-circumfused area in the region of the closely adjacent lead configuration and thus a relatively low inductance of this lead sector.
EP 0 609 528 also describes a method for reducing parasitic inductances in a parallel and closely adjacent DC leads of an individual switch. In this reference, the semiconductor components are arranged symmetrically on a substrate.
The prior art also includes power semiconductor modules in pressure contact technology. Examples of this technology can be found in DE 196 30 173 and DE 593 06 387. This type of power semiconductor module consists of ceramic substrates to which contact surfaces are applied, and on which semiconductor components are arranged.
The semiconductor components are connected to contact surfaces by soldering. The semiconductor components have bond connections to other semiconductor components or other second contact surfaces which are applied to the substrate and insulated against the first contact surface.
In this type of construction, pressure contacting relates to two different types of bonds. A first type of bond is the electrical bond of the leads with the associated contact surfaces of the substrate. The second type of bond is a thermal bond between the substrates or between the entire module and a cooling body. In these types of bonds, plastic elements can be used, which transfer pressure applied to the module from the outside, to the connecting elements and/or to the substrate to establish a secure electrical or thermal contact.
All low-inductance circuit arrangements described in prior art have in common that they achieve a certain reduction of parasitic inductances only in the partial areas of the overall system of intermediate circuit-rectifier. The best values that can thus be achieved for the overall inductance of this system are presently above 20 nH (nanohenry).
In EP 0 277 546, the transistors forming the individual switch are in close proximity to each other, and yet the current can flow through the circuit arrangement along different paths, and in particular, along paths of different lengths. This current flow causes different current-circumfused areas and also different inductances for the different conduction paths. Current-circumfused means that the current flows around a certain area. In drawings referring to a current-circumfused area, the current-circumfused area may be represented as a shaded section.
Unfortunately, the design of a half-bridge with this type of individual switches can never be low-inductance because of the necessary external circuitry. Taking all characteristics together, these designs may lead to a certain reduction in the parasitic inductances of the overall system intermediate circuit/DC/AC converter. However, this reduction still does not meet all the consumer and design requirements of minimizing parasitic inductances.
Particularly, DE 39 37 045 fails to meet the goal of minimizing parasitic inductance for two major reasons. The first reason is that the DC leads are not arranged at a minimal distance from each other, since the AC lead is arranged between the two DC leads. Thus the current-circumfused area in the region of the DC leads is not minimal, and the inductances for this region are correspondingly not minimal. The second reason is that the power transistors of the first and second power switches are arranged relatively far distant from each other, which also increases the parasitic inductances.
Referring now to FIG. 1, showing a typical design of a half-bridge intermediate circuit. The intermediate circuit includes a capacitor 1 with at least one positive lead 2, at least one negative lead 3, and at least one power switch 4.
Power switches 4 may be designed as MOSFETs or IGBTs. If power switches 4 are designed as IGBTs, an additional free-running diode 5 is required on each power switch 4. An AC lead 6 is supplied between power switches 4. A current flow 7 occurs from positive lead 2 to negative lead 3 during a commutation process. Current flow 7 flows around a current-circumfused area 8. The size of current-circumfused area 8 is a direct measure for the parasitic inductances which occur and illustrates the cross section of a coil with one winding.
Additionally referring now to FIG. 2 showing a realistic case of circuit arrangement similar to FIG. 1 where first and second power switches 4 include several parallel-connected power transistors. As a result of the additional power transistors, current flow 7 and current-circumfused area 8 are different. This design emphasizes that since the shape of current-circumfused area 8 changes relative to the additional transistors, the associated inductances for each power transistor are different.
Additionally referring now FIG. 3, a ceramic substrate 9 supports a positive lead 17 having as a positive surface a copper laminated surface 12. Ceramic substrate 9 also supports a negative lead 16 with a copper laminated surface 10 and an AC lead 18 with a copper laminated surface 11. For simplicity, auxiliary connections such as a gate, a base, or auxiliary emitters, are not shown.
On the plus area are multiple first power transistors 13 which constitute a first power switch, and a free-running diode 14. Bond wires 15 connect emitters of the power transistors to surface 11 of AC lead 18.
Arranged on surface 11 of AC lead 18 are second power transistors 19 as well as a second free-running diode. Bond wires 15 connect second power transistors 19 to the copper laminated surface 10 of negative lead 16.
Positive lead 17, negative lead 16 and AC lead 18 are also arranged on each respective surface matching their polarity. Typical for such arrangements, according to prior art, is an arrangement where positive and negative leads are already in close proximity, at least up to a short distance above the substrate. Here, current flow 7 indicates the maximum current-circumfused area. This area correspondingly determines the parasitic inductance of the circuit arrangement. With such circuit arrangements typical inductances in the range of 20 to 50 nH can be achieved in relation to the plane of the substrate.
Additionally referring now to FIG. 5, each of the respective copper laminated surfaces for each respective lead is positioned on substrate 9. Here, first power transistor 13 is on the positive surface 12 of positive lead 17 (not shown in this figure). Second power transistor 19 is on AC surface 11 of AC lead 18 (not shown in this figure).
Bond wires 15 connect the emitter of first power transistor 13 to copper laminates surface 11 of AC lead 18. Bond wires 15 also connect the emitter of second power transistor 19 to copper laminates surface 10 of negative lead 16 (not shown in this figure). An area 24, is current-circumfused in the plane (as shown), and is understood to extend below positive lead 17 (and surface 12) to the surface of substrate 9, or from the region of the bond connections up to a plain with surface 12 and beyond. A positive lead 20 joins positive lead surface 12 and a negative lead 21 joins negative lead surface 10
An object of the present invention is to optimize the parasitic inductances of a circuit arrangement in the region of the leads.
Another object of the present invention is to optimize parasitic inductances in a circuit in the region of the semiconductor components, arranged on an electrically insulating substrate.
Another object of the present invention is to optimize parasitic inductance in a circuit, so that the total inductance of the arrangement is at a magnitude of 2 nH or smaller, i.e. at least one order of magnitude below that of the prior art.
The present invention relates to a circuit with low parasitic inductances, reduced current flow paths, and reduced current-circumfusion. The circuit includes a ceramic substrate supporting mutually insulated metallic connection webs and a first and a second series-connected power switch. Each power switch includes a first and a second power transistor connected in parallel and DC and AC leads. The insulation layer separates the conduction webs from a supporting substrate and is effective to minimize any parasitic inductances in the circuit arrangement.
According to an embodiment of the present invention there is provided, a circuit, comprising: an substrate, a plurality of webs on the substrate, each web being a mutually insulated metallic connection web, an insulation layer between each web and the substrate, each web joining at least a first and a second power switch, the first and the second power switch connected in series, each first and second power switch including at least a first and a second power transistor, at least a first and a second DC lead, and at least a first AC lead, the first and second power transistors electrically connected in parallel, the first power transistor proximate each respective second power transistor in a row on the substrate, the at least first and second DC leads and the at least first AC joining the at least one first and second power transistor effective to enable an electrical connection through the circuit, the at least first and second DC leads positioned proximate each other in at least a first strip section and having at least a first portion parallel a support surface of the substrate, at least one of the first and the second DC leads in a second strip section parallel the support surface of the substrate and joining at least one of the plurality of webs effective to minimize a current flow path in the circuit, and the at least one of the plurality of webs has at least one contact point with the substrate effective to minimize a current-circumfused area in the circuit and reduce corresponding parasitic circuit inductance.
According to another embodiment of the present invention there is provided, a circuit, wherein: the plurality of webs arrayed between each respective first and second power transistors, and at least one of the first and the second DC leads is effective as a pressure-transmitting element to an external pressure-contact model.
According to another embodiment of the present invention there is provided, a circuit, wherein: the first and the second power switches are symmetrical to a center axis of the substrate and adjacent along a respective first and a second row of the first and the second power transistors.
According to another embodiment of the present invention there is provided, a circuit, wherein: the first and the second power transistors are one of a MOSFET-type and a IBGT-type transistor.
According to another embodiment of the present invention there is provided, a circuit, further comprising: at least a first free-running diode on each the first and the second row of respective the first and second power transistors.
According to another embodiment of the present invention there is provided, a circuit, wherein: the first and the second power transistors are the other of the MOSFET-type and the IBGT-type transistor.
According to another embodiment of the present invention there is provided, a circuit, wherein: the plurality of webs is effective to reduce a total inductance in the circuit to at or below 2 nH.
According to another embodiment of the present invention there is provided, a circuit, comprising: an substrate, a means for reducing parasitic inductance in the circuit, the means for reducing on the substrate, an insulation layer between the substrate and the means for reducing, the means for reducing joining at least a first and a second power switch, the first and the second power switch connected in series, each of the first and the second power switch including at least a first and a second power transistor, at least a first and a second DC lead, and at least a first AC lead, the first and second power transistors electrically connected in parallel, each the first power transistor proximate each respective the second power transistor in a row on the substrate, the at least first and second DC leads and the at least first AC joining the at least one first and the second power transistor effective to enable an electrical connection through the circuit, the at least first DC lead proximate the and second DC leads in at least a first strip section and having at least a first portion, the first strip portion parallel a support surface of the substrate, at least one of the first and the second DC lead in a second strip section parallel the support surface of the substrate and joining to the means for reducing effective to minimize a current flow path in the circuit, and the means for reducing has at least one contact point with the substrate effective to minimize a current-circumfused area in the circuit and reduce corresponding parasitic circuit inductance.
According to another embodiment of the present invention there is provided, a circuit, wherein: the means for reducing parasitic inductance is effective to reduce a total inductance in the circuit to at or below 2 nH.
According to another embodiment of the present invention there is provided, a circuit, wherein: the means for reducing includes a plurality of webs, each the web being a mutually insulated metallic connection web, and each the web between each the first and second power transistor.
The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements.